View ADM4210-1AUJZ-RL7_2485475.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hot swap controller in 6-lead tsot package adm4210 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features controls supply rails from 2.7 v to 16.5 v allows protected board removal and insertion to a live backplane external sense resistor provides adjustable analog current limit with circuit breaker peak fault current limited with fast response charge pumped gate drive for external n-fet switch automatic retry or latch-off during current fault undervoltage lockout low profile (1 mm), 6-lead, tsot package pin compatible with ltc4210-1 and ltc4210-2 applications hot swap board insertion: line cards, raid systems industrial high-side switches/circuit breakers electronic circuit breakers general description the adm4210 is a hot swap controller that safely enables a printed circuit board to be removed and inserted to a live backplane. this is achieved using an external n-channel power mosfet with a current control loop that monitors the load current through a sense resistor. an internal charge pump is used to enhance the gate of the n-channel fet. when an overcurrent condition is detected, the gate voltage of the fet is reduced to limit the current flowing through the sense resistor. during an overcurrent condition, the timer cap determines the amount of time the fet remains at a current limiting mode of operation until it is shut down. the on (on- clr ) pin is the enable input for the device and can be used to monitor the input supply voltage. the adm4210 operates with a supply voltage ranging from 2.7 v to 16.5 v. the adm4210 is available in two options: the adm4210-1 with automatic retry for overcurrent fault and the adm4210-2 with latch off for an overcurrent fault. toggling the on (on- clr ) pin resets a latched fault. the adm4210 is packaged in a 6-lead tsot. functional block diagram long v in = 5v v out = 5v v cc r sense 0.01 ? q 1 c timer 0.22f c timer gate long 1.3v short sense gate drive/ logic on timer adm4210 gnd gnd gnd r on1 20k ? r g 100 ? r c 100 ? c c 0.01f r on2 10k ? c load 470f 05132-001 + figure 1. 05132-050 10ms/div v on (2v/div) v timer (1v/div) v out (5v/div) i out (0.5a/div) c load = 470f figure 2. start-up sequence
adm4210 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 thermal characteristics .............................................................. 4 esd caution.................................................................................. 4 pin configurations and function descriptions ........................... 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 11 overview...................................................................................... 11 uvlo........................................................................................... 11 on (on- clr ) pin..................................................................... 11 gate ........................................................................................... 11 current limit function............................................................. 11 calculating the current limit .................................................. 11 circuit breaker function........................................................... 12 timer function........................................................................... 12 power-up timing cycle ............................................................ 12 circuit breaker timing cycle................................................... 13 automatic retry or latched off............................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 7/06revision 0: initial version
adm4210 rev. 0 | page 3 of 16 specifications v cc = 2.7 v to 16.5 v, t a = ?40c to +85c, typical values at t a = 25c, unless otherwise noted. table 1. parameter symbol min typ max unit conditions v cc pin operating voltage range v cc 2.7 16.5 v supply current i cc 0.65 3.5 ma undervoltage lockout v uvlo 2.2 2.5 2.65 v v cc rising undervoltage lockout hysteresis v uvlohys 100 mv on (on- clr ) pin input current i inon ?10 0 +10 a threshold v on 1.22 1.3 1.38 v on rising threshold hysteresis v onhyst 80 mv sense pin input current i insense ?10 +5 +10 a v sense = v cc circuit breaker limit voltage v cb 44 50 56 mv v cb = (v cc ? v sense ) gate pin pull-up current i gateup ?5 ?10 ?15 a v gate = 0 v pull-down current i gatedn 25 ma v timer = 1.5 v, v gate = 3 v or v on = 0 v, v gate = 3 v or v cc ? v sense = 100 mv, v gate = 3 v gate drive voltage v gate 4.5 7.5 10 v v gate ? v cc , v cc = 3 v 5.0 8.5 12 v v gate ? v cc , v cc = 3.3 v 8.75 12 16 v v gate ? v cc , v cc = 5 v 7.6 12 16 v v gate ? v cc , v cc = 12 v 6.0 11 18 v v gate ? v cc , v cc = 15 v timer pin pull-up current i timerup ?2 ?5 ?8.5 a initial cycle, v timer = 1 v ?25 ?60 ?100 a during current fault, v timer = 1 v pull-down current i timerdn 2 3.5 a after current fault, v timer = 1 v 100 a normal operation, v timer = 1 v threshold high v timerh 1.22 1.3 1.38 v timer rising threshold low v timerl 0.15 0.2 0.25 v timer falling t off turn-off time (timer rise to gate fall) t off(tmrhigh) 1 s v timer = 0 v to 2 v step, v cc = v on = 5 v turn-off time (on (on- clr ) fall to gate fall) t off(onlow) 30 s v on = 5 v to 0 v step, v cc = 5 v turn-off time (v cc rise to ic reset) t off(vcclow) 30 s v cc = 0 v to 2 v step, v on = 5 v
adm4210 rev. 0 | page 4 of 16 absolute maximum ratings table 2. parameter rating v cc pin ?0.3 v to +20 v sense pin ?0.3 v to +20 v v cc ? sense 5 v timer pin ?0.3 v to (v cc + 0.3 v) on (on- clr ) pin ?0.3 v to +20 v gate pin ?0.3 v to (v cc + 11 v) storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 6-lead tsot 169.5 c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adm4210 rev. 0 | page 5 of 16 pin configurations and function descriptions on timer 1 gnd 2 3 v cc 6 gate 4 sense 5 adm4210-1auj top view (not to scale) 05132-006 figure 3. pin configuration, 1auj model on-clr timer 1 gnd 2 3 v cc 6 gate 4 sense 5 a dm4210-2auj top view (not to scale) 05132-007 figure 4. pin configuration, 2auj model table 4. pin function descriptions pin no. mnemonic description 1 timer timer input pin. the initial and circuit breaker timing cycles are set by this external capacitor. the initial timing delay is 272.9 ms/f, and 21.7 ms/f for a circuit breaker delay. when the timer pin is pulled beyond the upper threshold, the gate turns off. 2 gnd chip ground pin. 3 on (on- clr ) input pin. the on (on- clr ) pin is an input to a comparator that has a low-to-high threshold of 1.3 v with 80 mv hysteresis and a glitch filter. th e adm4210 is reset when the on (on- clr ) pin is low. when the on (on- clr ) pin is high, the adm4210 is enabled. a rising edge on this pin ha s the added function of clearing a fault and restarting the device on the latched off model, the adm4210-2. 4 gate gate output pin. an internal charge pump provides a 12 a pull-up current to drive the gate of an n-channel mosfet. in an overcurrent condition, the adm4210 cont rols the external fet to maintain a constant load current. 5 sense current limit sense input pin. the current limit is set via a sense resistor between the v cc and sense pins. in an overcurrent condition, the gate of the fet is controlled to maintain the sense voltage at 50 mv. when this limit is reached, the timer circuit breaker mode is activated. the circuit breaker limit can be disabled by connecting the v cc pin and sense pin together. 6 v cc positive supply input pin. the adm4210 operates between 2.7 v to 16.5 v. an unde rvoltage lockout (uvlo) circuit with a glitch filter resets the adm4210 when th e supply voltage drops below the specified uvlo limit.
adm4210 rev. 0 | page 6 of 16 supply voltage (v) supply current (ma) typical performance characteristics 4.0 0 01 8 25 0 01 8 supply voltage (v) gate voltage (v) 246810121416 t a = 25c 05132-032 3.5 3.0 2.5 2.0 1.5 1.0 0.5 figure 5. supply current vs. supply voltage 1.0 0 ?50 150 temperature (c) supply current (ma) 0.8 0.6 0.4 0.2 ?25 0 25 50 75 100 125 v cc = 15v v cc = 12v v cc = 5v v cc = 3v 0.9 0.7 0.5 0.3 0.1 05132-033 figure 6. supply current vs. temperature 2.65 2.45 ?50 150 temperature (c) uvlo threshold (v) v cc = 5v ?25 0 25 50 75 100 125 2.63 2.61 2.59 2.57 2.55 2.53 2.51 2.49 2.47 v cc falling v cc rising 05132-046 figure 7. uvlo threshold vs. temperature 246810121416 20 15 10 5 05132-013 figure 8. gate voltage vs. supply voltage 25 0 ?50 150 temperature (c) gate voltage (v) 20 15 10 5 ?25 0 25 50 75 100 125 v cc = 15v v cc = 12v v cc = 5v v cc = 3v 05132-015 figure 9. gate voltage vs. temperature ? 8 ?14 01 supply voltage (v) gate current (a) 8 ?9 ?10 ?11 ?12 ?13 246810121416 05132-009 figure 10. gate current (up) vs. supply voltage
adm4210 rev. 0 | page 7 of 16 ? 11.0 ?13.0 ?50 150 temperature (c) gate current (a) ?25 0 25 50 75 100 125 v cc = 15v v cc = 12v v cc = 5v v cc = 3v ?11.2 ?11.4 ?11.6 ?11.8 ?12.0 ?12.2 ?12.4 ?12.6 ?12.8 05132-017 figure 11. gate current (up) vs. temperature 10 0 01 8 supply voltage (v) delta gate voltage (v) 246810121416 9 8 7 6 5 4 3 2 1 05132-014 figure 12. delta gate voltage vs. supply voltage 10 0 ?50 150 temperature (c) delta gate voltage (v) ?25 0 25 50 75 100 125 v cc = 15v v cc = 12v v cc = 5v v cc = 3v 9 8 7 6 5 4 3 2 1 05132-016 figure 13. delta gate voltage vs. temperature 0 ?10 01 supply voltage (v) i timerup (a) 8 246810121416 t a = 25c ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 05132-035 figure 14. i timerup (in initial cycle) vs. supply voltage 0 ?10 ?50 150 temperature (c) i timerup (a) v cc = 5v ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?25 0 25 50 75 100 125 05132-038 figure 15. i timerup (in initial cycle) vs. temperature ? 20 ?100 01 supply voltage (v) i timerup (a) 8 246810121416 t a = 25c ?30 ?40 ?50 ?60 ?70 ?80 ?90 05132-036 figure 16. i timerup (during cct breaker delay) vs. supply voltage
adm4210 rev. 0 | page 8 of 16 ? 20 ?100 ?50 150 temperature (c) i timerup (a) v cc = 5v ?25 0 25 50 75 100 125 ?30 ?40 ?50 ?60 ?70 ?80 ?90 05132-039 figure 17. i timerup (during cct breaker delay) vs. temperature 3.0 1.0 01 8 supply voltage (v) i timerdn (a) 246810121416 t a = 25c 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 05132-034 figure 18. i timerdn (in cool-off cycle) vs. supply voltage 3.0 1.0 ?50 150 temperature (c) i timerdn (a) v cc = 5v 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 ?25 0 25 50 75 100 125 05132-037 figure 19. i timerdn (in cool-off cycle) vs. temperature 1.38 1.22 01 supply voltage (v) timer high threshold (v) 8 246810121416 t a = 25c 1.36 1.34 1.32 1.30 1.28 1.26 1.24 05132-042 figure 20. timer high th reshold vs. supply voltage 1.38 1.22 ?50 150 temperature (c) timer high threshold (v) v cc = 5v ?25 0 25 50 75 100 125 1.36 1.34 1.32 1.30 1.28 1.26 1.24 05132-044 8 figure 21. timer high threshold vs. temperature 0.24 0.16 01 supply voltage (v) timer low threshold (v) 246810121416 t a = 25c 0.23 0.22 0.21 0.20 0.19 0.18 0.17 05132-043 figure 22. timer low threshold vs. supply voltage
adm4210 rev. 0 | page 9 of 16 0.24 0.16 ?50 150 temperature (c) timer low threshold (v) v cc = 5v ?25 0 25 50 75 100 125 0.23 0.22 0.21 0.20 0.19 0.18 0.17 05132-045 figure 23. timer low threshold vs. temperature 1.45 1.05 01 8 supply voltage (v) on (on-clr) pin threshold (v) 246810121416 t a = 25c 1.40 1.35 1.30 1.25 1.20 1.15 1.10 low threshold high threshold 05132-040 figure 24. on (on- clr ) pin threshold vs. supply voltage 1.45 1.05 ?50 150 temperature (c) on (on-clr) pin threshold (v) v cc = 5v ?25 0 25 50 75 100 125 1.40 1.35 1.30 1.25 1.20 1.15 1.10 high threshold low threshold 05132-041 figure 25. on (on- clr ) pin threshold vs. temperature 80 0 01 8 supply voltage (v) t off(onlow) (s) t a = 25c 70 60 50 40 30 20 10 05132-047 246810121416 figure 26. t off(onlow) vs. supply voltage
adm4210 rev. 0 | page 10 of 16 80 0 ?50 150 temperature (c) t off(onlow) (s) ?25 0 25 50 75 100 125 v cc = 15v v cc = 12v v cc = 5v v cc = 3v 70 60 50 40 30 20 10 05132-048 figure 27. t off(onlow) vs. temperature 50 40 01 supply voltage (v) v cb (mv) 8 49 48 47 46 45 44 43 42 41 246810121416 05132-049 figure 28. cct breaker voltage vs. supply voltage 50 0 ?50 150 temperature (c) v cb (mv) ?25 0 25 50 75 100 125 45 40 35 30 25 20 15 10 5 05132-021 figure 29. cct breaker voltage vs. temperature
adm4210 rev. 0 | page 11 of 16 theory of operation many systems require the insertion or removal of circuit boards to live backplanes. during this event, the supply bypass and hold- up capacitors can require substantial transient currents from the backplane power supply as they charge. these currents can cause permanent damage to connector pins or undesirable glitches and resets to the system. the adm4210 is intended to control the powering of a system (on and off) in a controlled manner, allowing the board to be removed from, or inserted into, a live backplane by protecting it from excess currents. the adm4210 can reside either on the backplane or on the removable board. overview the adm4210 operates over a supply range of 2.7 v to 16.5 v. as the supply voltage is coming up, an undervoltage lockout circuit checks if sufficient supply voltage is present for proper operation. during this period, the fet is held off by the gate pin being held to gnd. when the supply voltage reaches a level above uvlo and the on (on- clr ) pin is high, an initial timing cycle ensures that the board is fully inserted in the backplane before turning on the fet. the timer pin capacitor sets the periods for all of the timer pin functions. after the initial timing cycle, the adm4210 monitors the inrush current through an external sense resistor. overcurrent conditions are actively limited to 50 mv/r sense for the circuit breaker timer limit. the adm4210-1 automatically retries after a current limit fault and the adm4210-2 latches off. the retry duty cycle on the adm4210-1 timer function is limited to 3.8% for fet cooling. uvlo if the v cc supply is too low for normal operation, an under- voltage lockout circuit holds the adm4210 in reset. the gate pin is held to gnd during this period. when the supply reaches this uvlo voltage, the adm4210 starts when the on (on- clr ) pin condition is satisfied. on (on-clr ) pin the on (on- clr ) pin is the enable pin. it is connected to a comparator that has a low-to-high threshold of 1.3 v with 80 mv hysteresis and a glitch filter. the adm4210 is reset when the on (on- clr ) pin is low. when the on (on- clr ) pin is high, the adm4210 is enabled. a rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model, the adm4210-2. a low input on the on (on- clr ) pin turns off the external fet by pulling the gate pin to ground and resets the timer. an external resistor divider at the on (on- clr ) pin can be used to program an undervoltage lockout value higher than the internal uvlo circuit. there is a glitch filter delay of approximately 3 s on rising allowing the addition of an rc filter at the on (on- clr ) pin to increase the delay time at card insertion. if using a short pin system to enable the device, a pull-down resistor should be used to hold the device prior to insertion. gate gate drive for the external n-channel mosfet is achieved using an internal charge pump. the gate driver consists of a 12 a pull-up from the internal charge pump. there are various pull-down devices on this pin. at a hot swap condition the board is hot inserted to the supply bus. during this event, it is possible for the external fet gate capacitance to be charged up by the sudden presence of the supply voltage. this can cause uncontrolled inrush currents. an internal strong pull-down circuit holds gate low while in uvlo. this reduces current surges at inser- tion. after the initial timing cycle, the gate is then pulled high. during an overcurrent condition, the adm4210 servos the gate pin in an attempt to maintain a constant current to the load until the circuit breaker timeout completes. in the event of a timeout, the gate pin abruptly shuts down using the 4 ma pull-down device. care must be taken not to load the gate pin resistively because this reduces the gate drive capability. current limit function the adm4210 features a fast response current control loop that actively limits the current by reducing the gate voltage of the external fet. this current is measured by monitoring the voltage drop across an external sense resistor. the adm4210 tries to regulate the gate of the fet to achieve a 50 mv voltage drop across the sense resistor. calculating the current limit the sense resistor connected between v cc and the sense pin is used to determine the nominal fault current limit. this is given by the following equation: ilimit nom = vcb nom / rsense nom (1) the minimum load current is given by equation 2 ilimit min = vcb min /rsense max (2) the maximum load current is given by equation 3 ilimit max = vcb max / rsense min (3) for proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. the sense resistor power rating must exceed ( vcb max ) 2 / rsense min
adm4210 rev. 0 | page 12 of 16 circuit breaker function when the supply experiences a sudden current surge, such as a low impedance fault on load, the bus supply voltage can drop significantly to a point where the power to an adjacent card is affected, potentially causing system malfunctions. the adm4210 limits the current drawn by the fault by reducing the gate voltage of the external fet. this minimizes the bus supply voltage drop caused by the fault and protects neighboring cards. as the voltage across the sense resistor approaches the current limit, a timer activates. this timer resets again if the sense voltage returns below this level. if the sense voltage is any voltage below 44 mv, the timer is guaranteed to be off. should the current continue to increase, the adm4210 tries to regulate the gate of the fet to achieve a limit of 50 mv across the sense resistor. however, if the device is unable to regulate the fault current and the sense voltage further increases, a larger pull- down, in the order of milliamperes, is enabled to compensate for fast current surges. if the sense voltage is any voltage greater than 56 mv, this pull-down is guaranteed to be on. when the timer expires, the gate pin shuts down. timer function the timer pin is responsible for several key functions on the adm4210. a capacitor controls the initial power on reset time and the amount of time an overcurrent condition lasts before the fet shuts down. on the adm4210-1, the timer pin also controls the time between auto retry pulses. there are pull-up and pull-down currents internally available to control the timer functions. the voltage on the timer pin is compared with two threshold voltages: comp1 (0.2 v) and comp2 (1.3 v). the four timing currents are listed in table 5 . table 5. timing current level (a) pull-up 5 pull-up 60 pull-down 2 pull-down 100 power-up timing cycle the adm4210 is in reset when the on (on- clr ) pin is held low. the gate pin is pulled low and the timer pin is pulled low with a 100 a pull-down. at time point 2 in figure 30 , the on (on- clr ) pin is pulled high. for the device to startup correctly, the supply voltage must be above uvlo, the on (on- clr ) pin must be above 1.3 v, and the timer pin voltage must be less than 0.2 v. the initial timing cycle begins when these three conditions are met, and the timer pin is pulled high with 5 a. at time point 3, the timer reaches the comp2 threshold. this is the end of the first section of the initial cycle. the 100 a current source then pulls down the timer pin until it reaches 0.2 v at time point 4. the initial cycle delay (time point 2 to time point 4) relates to c timer by equation t initial = 1.3 c timer /5 a (4) when the initial cycle ends, a start-up cycle activates and the gate pin is pulled high; the timer pin continues to pull down. 1 2 normal cycle initial cycle start-up cycle reset mode 3 4 v in v on v timer v gate v out 05126-002 figure 30. power-up timing 2a 5a 60a 100a v in v on v timer v gate v out i rsense normal cycle initial cycle start-up cycle reset mode 05126-003 figure 31. power-up into capacitor
adm4210 rev. 0 | page 13 of 16 circuit breaker timing cycle automatic retry or latched off when the voltage across the sense resistor exceeds the circuit breaker trip voltage, the 60 a timer pull-up current is activated. if the sense voltage falls below this level before the timer pin reaches 1.3 v, the 60 a pull-up is disabled and the 2 a pull- down is enabled. this is likely to happen if the overcurrent fault is only transient, such as an inrush current. this is shown in figure 31 . however, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 a pull-up remains active. this allows the timer pin to reach the high trip point of 1.3 v and initiate the gate shutdown. on the adm4210-2, the timer pin continues pulling up but switches to the 5 a pull-up when it reaches the 1.3 v threshold. the device can be reset by toggling the on- clr pin or by manually pulling the timer pin low. on the adm4210-1, the timer pin activates the 2 a pull-down once the 1.3 v threshold is reached, and continues to pull down until it reaches the 0.2 v threshold. at this point, the 100 a pull-down is activated and the gate pin is enabled. the device keeps retrying in the manner as shown in figure 32 . the adm4210 is available in two models. the adm4210-1 has an automatic retry system whereby when a current fault is detected, the fet is shut down after a time determined by the timer capacitor, and it is switched on again in a controlled con- tinuous cycle to determine if the fault remains (see figure 32 for details). the period of this cycle is determined by the timer capacitor at a duty cycle of 3.8% on and 96.2% off. the adm4210-2 model has a latch off system whereby when a current fault is detected, the gate is switched off after a time determined by the timer capacitor (see figure 33 for details). toggling the on- clr pin, or pulling the timer pin to gnd for a brief period, resets this condition. 5a comp1 comp2 short- circuit event 60a v timer v out v gsfet i rsense 05126-005 the duty cycle of this automatic retry cycle is set to the ratio of 2 a/60 a, which approximates 3.8% on. the value of the timer capacitor determines the on time of this cycle. this time is calculated as follows: t on = 1.3 c timer /60 a t off = 1.1 c timer /2 a 2a comp1 comp2 short- circuit event 60a 100a v timer v out v gsfet i rsense fault cycle fault cycle 0 5126-004 figure 33. adm4210-2 latch off after overcurrent fault figure 32. adm4210-1 automatic retry during overcurrent fault
adm4210 rev. 0 | page 14 of 16 outline dimensions 13 45 2 6 2.90 bsc 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 8 4 0 0.50 0.30 0.10 max * 0.90 0.87 0.84 seating plane * 1.00 max 0.60 0.45 0.30 pin 1 indicato r * compliant to jedec standards mo-193-aa with the exception of package height and thickness. figure 34. 6-lead thin small outline transistor package [tsot] (uj-6) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADM4210-1AUJZ-RL7 1 ? 40c to +85c 6-lead tsot uj-6 m2p adm4210-2aujz-rl7 1 ? 40c to +85c 6-lead tsot uj-6 m2q 1 z = pb-free part.
adm4210 rev. 0 | page 15 of 16 notes
adm4210 rev. 0 | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05132-0-7/06(0)

▲Up To Search▲

Price & Availability of ADM4210-1AUJZ-RL7

	To Download ADM4210-1AUJZ-RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .